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altera corporation 311 max 5000 programmable logic device family june 1996, ver. 3 data sheet a-ds-m5000-03 features... n advanced multiple array matrix (max) 5000 architecture combining speed and ease-of-use of pal devices with the density of programmable gate arrays n complete family of high-performance, erasable cmos eprom eplds for designs ranging from fast 28-pin address decoders to 100-pin lsi custom peripherals n 600 to 3,750 usable gates (see table 1 ) n fast, 15-ns combinatorial delays and 83.3-mhz counter frequencies n configurable expander product-term distribution allowing more than 32 product terms in a single macrocell n 28 to 100 pins available in dip, j-lead, pga, soic, and qfp packages n programmable registers providing d, t, jk, and sr flipflop functionality with individual clear, preset, and clock controls n programmable security bit for protection of proprietary designs n software design support featuring altera? max+plus ii development system on 486- or pentium-based pcs, and sun sparcstation, hp 9000 series 700, and ibm risc system/6000 workstations table 1. max 5000 device features feature epm5032 epm5064 epm5128 epm5130 epm5192 usable gates 600 1,250 2,500 2,500 3,750 macrocells 32 64 128 128 192 logic array blocks (labs) 148812 expanders 64 128 256 256 384 routing global pia pia pia pia maximum user i/o pins 24 36 60 68, 84 72 t pd (ns) 15 25 25 25 25 t asu (ns) 44444 t co (ns) 10 14 14 14 14 f cnt (mhz) 76.9 50 50 50 50
312 altera corporation max 5000 programmable logic device family data sheet ...and more features n programming support with altera? master programming unit (mpu) or programming hardware from other manufacturers n additional design entry and simulation support provided by edif, lpm, verilog hdl, vhdl, and other interfaces to popular eda tools from manufacturers such as cadence, data i/o, exemplar, mentor graphics, minc, orcad, synopsys, veribest, and viewlogic general description the max 5000 family combines innovative architecture and advanced process technologies to offer optimum performance, flexibility, and the highest logic-to-pin ratio of any general-purpose programmable logic device (pld) family. the max 5000 family provides 600 to 3,750 usable gates, pin-to-pin delays as fast as 15 ns, and counter frequencies of up to 83.3 mhz. see table 2 . the max 5000 architecture supports 100 % ttl emulation and high-density integration of multiple ssi, msi, and lsi logic functions. for example, an epm5192 device can replace over 100 74-series devices; it can integrate complete subsystems into a single package, saving board area and reducing power consumption. max 5000 eplds are available in a wide range of packages (see table 3 ), including the following: n windowed ceramic and plastic dual in-line (cerdip and pdip) n windowed ceramic and plastic j-lead chip carrier (jlcc and plcc) n windowed ceramic pin-grid array (pga) n plastic small-outline integrated circuit (soic) n ceramic and plastic quad flat pack (cqfp and pqfp) table 2. max 5000 timing parameter availability device speed ( t pd1 ) 15 ns 20 ns 25 ns 30 ns 35 ns epm5032 vvv epm5064 vvv epm5128 vvv epm5130 vv epm5192 vv
altera corporation 313 max 5000 programmable logic device family data sheet note: (1) contact altera for up to date information on package availability. max 5000 eplds have between 32 and 192 macrocells that are combined into groups called logic array blocks (labs). each macrocell has a programmable- and /fixed- or array and a configurable register that provides d, t, jk, or sr operation with independent programmable clock, clear, and preset functions. to build complex logic functions, each macrocell can be supplemented with shareable expander product terms (?hared expanders? to provide more than 32 product terms per macrocell. the max 5000 family is supported by altera? max+plus ii development system, a single, integrated package that offers schematic, text?ncluding the altera hardware description language (ahdl) and waveform design entry; compilation and logic synthesis; simulation and timing analysis; and device programming. max+plus ii provides edif 2 0 0 and 3 0 0, lpm, vhdl, verilog hdl, and other interfaces for additional design entry and simulation support from other industry- standard pc- and workstation-based eda tools. max+plus ii runs on 486- and pentium-based pcs, and sun sparcstation, hp 9000 series 700, ibm risc system/6000 workstations. f for more information, go to the max+plus ii programmable logic development system & software data sheet in this data book. table 3. max 5000 pin count & package options note (1) device pin count 28 44 68 84 100 epm5032 cerdip pdip jlcc plcc soic epm5064 jlcc plcc epm5128 jlcc plcc pga epm5130 jlcc plcc pga pqfp epm5192 jlcc plcc pga
314 altera corporation max 5000 programmable logic device family data sheet functional description this section provides a functional description of max 5000 eplds, which have the following architectural features: n logic array blocks n macrocells n clocking options n expander product terms n programmable interconnect array n i/o control blocks the max 5000 architecture is based on the concept of linking high- performance, ?xible logic array modules called logic array blocks (labs). multiple labs are linked via the programmable interconnect array (pia), a global bus that is fed by all i/o pins and macrocells. in addition to these basic elements, the max 5000 architecture includes 8 to 20 dedicated inputs, each of which can be used as a high-speed, general- purpose input. alternatively, one of the dedicated inputs can be used as a high-speed global clock for registers. logic array blocks max 5000 eplds contain 1 to 12 labs. the epm5032 has a single lab, while the epm5064, epm5128, epm5130, and epm5192 contain multiple labs. each lab consists of a macrocell array and an expander product- term array. see figure 1 . the number of macrocells and expanders in the arrays varies with each device.
altera corporation 315 max 5000 programmable logic device family data sheet figure 1. max 5000 architecture macrocells are the primary resource for logic implementation. additional logic capability is available from expanders, which can be used to supplement the capabilities of any macrocell. the expander product-term array consists of a group of unallocated, inverted product terms that can be used and shared by all macrocells in the lab to create combinatorial and registered logic. these flexible macrocells and shareable expanders facilitate variable product-term designs without the inflexibility of fixed product-term architectures. all macrocell outputs are globally routed within an lab via the lab interconnect. the outputs of the macrocells also feed the i/o control block, which consists of groups of programmable tri-state buffers and i/o pins. in the epm5064, epm5128, epm5130, and epm5192 devices, multiple labs are connected by a pia. all macrocells feed the pia to provide efficient routing for high-fan-in designs. expander product-term array lab interconnect macrocell array lab a pia 4 to 16 i/o pins per lab to all other labs i/o control block 8 to 20 dedicated inputs feedback from i/o pins to lab (single-lab devices) pia in multi-lab devices only 16 24
316 altera corporation max 5000 programmable logic device family data sheet macrocells the max 5000 macrocell consists of a programmable logic array and an independently configurable register (see figure 2 ). the register can be programmed to emulate d, t, jk, or sr operation, as a flow-through latch, or bypassed for combinatorial operation. combinatorial logic is implemented in the programmable logic array, in which three product terms that are ored together feed one input to an xor gate. the second input to the xor gate is used for complex xor arithmetic logic functions and for de morgan? inversion. the output of the xor gate feeds the programmable register or bypasses it for combinatorial operation. figure 2. max 5000 device macrocell additional product terms?alled secondary product terms?re used to control the output enable, preset, clear, and clock signals. preset and clear product terms drive the active-low asynchronous preset and asynchronous clear inputs to the configurable flipflop. the clock product term allows each register to have an independent clock and supports positive- and negative-edge-triggered operation. macrocells that drive an output pin can use the output enable product term to control the active- high tri-state buffer in the i/o control block. the max 5000 macrocell configurability makes it possible to efficiently integrate complete subsystems into a single device. prn clrn q 8 or 20 dedicated inputs 32 or 64 expander product terms 24 programmable interconnect signals (multi-lab devices only) output enable preset clear to i/o control block global clock (one per lab) programmable register i/o feedback macrocell feedback d array clock logic array
altera corporation 317 max 5000 programmable logic device family data sheet clocking options each lab supports either global or array clocking. global clocking is provided by a dedicated clock signal ( clk ) that offers fast clock-to-output delay times. since each lab has one global clock, all flipflop clocks within the lab can be positive-edge-triggered from the clk pin. if the clk pin is not used as a global clock, it can be used as a high-speed dedicated input. in the array clocking mode, each flipflop is clocked by a product term. any input pin or internal logic can be used as a clock source. array clocking allows each flipflop to be configured for positive- or negative- edge-triggered operation, giving the macrocell increased flexibility. systems that require multiple clocks are easily integrated into max 5000 eplds. each flipflop in an lab can be clocked by a different array-generated clock; however, global and array clocking modes cannot be mixed in the same lab. expander product terms while most logic functions can be implemented with the product terms available in each macrocell, some logic functions are more complex and require additional product terms. although additional macrocells can be used to supply the needed logic resources, the max 5000 architecture can also use shared expander product terms that provide additional product terms directly to any macrocell in the same lab. these expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed. each lab has 32 shared expanders (except for the epm5032 device, which has 64). the expanders can be viewed as a pool of uncommitted product terms. the expander product-term array (see figure 3 ) contains unallocated, inverted product terms that feed the macrocell array. expanders can be used and shared by all product terms in the lab. wherever extra logic is needed (including register control functions), expanders can be used to implement the logic. these expanders provide the flexibility to implement register- and product-term-intensive designs in max 5000 eplds.
318 altera corporation max 5000 programmable logic device family data sheet figure 3. expander product terms expanders are fed by all signals in the lab. one expander can feed all macrocells in the lab or multiple product terms in the same macrocell. since expanders also feed the secondary product terms of each macrocell, complex logic functions can be implemented without using additional macrocells. expanders can also be cross-coupled to build additional flipflops, latches, or input registers. a small delay ( t sexp ) is incurred when shared expanders are used. programmable interconnect array the higher-density max 5000 devices?pm5064, epm5128, epm5130, and epm5192?se a programmable interconnect array (pia) to route signals between the various labs. the pia, which is fed by all macrocell and i/o pin feedbacks, routes only the signals required for implementing logic in an lab. while the routing delays of channel-based routing schemes in masked or field-programmable gate arrays (fpgas) are cumulative, variable, and path-dependent, the max 5000 pia has a fixed delay. the pia thus eliminates skew between signals and makes timing performance easy to predict. i/o control blocks each lab has an i/o control block that allows each i/o pin to be individually configured for input, output, or bidirectional operation. see figure 4 . the i/o control block is fed by the macrocell array. a dedicated macrocell product term controls a tri-state buffer, which drives the i/o pin. 8 or 20 dedicated inputs 32 or 64 expander product terms 24 programmable interconnect signals (multi-lab devices only) to macrocell array macrocell feed backs
altera corporation 319 max 5000 programmable logic device family data sheet figure 4. i/o control block the max 5000 architecture provides dual i/o feedback in which macrocell and i/o pin feedbacks are independent, allowing maximum flexibility. when an i/o pin is configured as an input, the associated macrocell can be used for buried logic. using an i/o pin as an input in single-lab devices reduces the number of available expanders by two. in multi-lab devices, i/o pins feed the pia directly. design security all max 5000 eplds contain a programmable security bit that controls access to the data programmed into the device. when this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. this feature provides a high level of design security, since programmed data within eprom cells is invisible. the security bit that controls this function, as well as all other program data, is reset when an epld is erased. generic testing max 5000 eplds are fully functionally tested. complete testing of each programmable eprom bit and all internal logic elements ensures 100 % programming yield. ac test measurements are taken under conditions equivalent to those in figure 5 . figure 5. ac test conditions oe control (from macrocell product term) from macrocell array macrocell feedback i/o pin feedback power supply transients can affect ac measurements. simultaneous transitions of multiple outputs should be avoided for accurate measurement. threshold tests must not be performed under ac conditions. large-amplitude, fast ground- current transients normally occur as the device outputs discharge the load capacitances. when these transients ?w through the parasitic inductance between the device ground pin and the test system ground, signi?ant reductions in observable noise immunity can result. vcc to test system c1 (includes jig capacitance) device input rise and fall times < 3 ns 464 w device output 250 w
320 altera corporation max 5000 programmable logic device family data sheet test patterns can be used and then erased during early stages of the device production flow. eprom-based eplds in one-time-programmable windowless packages also contain on-board logic test circuitry to allow verification of function and ac specifications during the production flow. device programming all max 5000 eplds can be programmed on 486- and pentium-based pcs with an altera logic programmer card, the master programming unit (mpu), and the appropriate device adapter. the mpu checks continuity to ensure adequate electrical contact between the adapter and the device. f for more information, see altera programming hardware data sheet in this data book. max+plus ii software can use text- or waveform-format test vectors created with the max+plus ii text or waveform editor to test a programmed device. for added design verification, designers can perform functional testing to compare the functional behavior of a max 5000 epld with the simulation results. (this feature requires a device adapter with the ?lm-?prefix.) data i/o and other programming hardware manufacturers also offer programming support for altera devices. f for more information, see programming hardware manufacturers in this data book. qfp carrier & development socket max 5000 devices in 100-pin qfp packages are shipped in special plastic carriers to protect the fragile qfp leads. each carrier can be used with a prototype development socket and programming hardware available from altera or data i/o. this carrier technology makes it possible to program, test, erase, and reprogram devices without exposing the leads to mechanical stress. f for detailed information and carrier dimensions, refer to the qfp carrier & development socket data sheet in this data book.
altera corporation 321 max 5000 programmable logic device family data sheet max 5000 device absolute maximum ratings note (1) max 5000 device recommended operating conditions max 5000 device dc operating conditions note (5) epm5032 max 5000 device capacitance epm5064, epm5128, epm5130 & epm5192 max 5000 device capacitance symbol parameter conditions min max unit v cc supply voltage with respect to gnd ?.0 7.0 v v i dc input voltage note (2) ?.0 7.0 v i out dc output current, per pin ?5 25 ma t stg storage temperature no bias ?5 135 c t amb ambient temperature under bias ?5 135 c t j junction temperature ceramic packages, under bias 150 c plastic packages, under bias 135 c symbol parameter conditions min max unit v cc supply voltage notes (3) , (4) 4.75 (4.5) 5.25 (5.5) v v i input voltage 0v cc v v o output voltage 0v cc v t a operating temperature for commercial use 0 70 c t a operating temperature for industrial use ?0 85 c t r input rise time 100 ns t f input fall time 100 ns symbol parameter conditions min typ max unit v ih high-level input voltage note (3) 2.0 v cc + 0.3 v v il low-level input voltage ?.3 0.8 v v oh high-level ttl output voltage i oh = ? ma dc, note (6) 2.4 v v ol low-level output voltage i ol = 8 ma dc, note (6) 0.45 v i i input leakage current v i = v cc or gnd ?0 10 m a i oz tri-state output off-state current v o = v cc or gnd ?0 40 m a symbol parameter conditions min max unit c in input pin capacitance v in = 0 v, f = 1.0 mhz 10 pf c io i/o pin capacitance v out = 0 v, f = 1.0 mhz 12 pf symbol parameter conditions min max unit c in input pin capacitance v in = 0 v, f = 1.0 mhz 10 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 20 pf
322 altera corporation max 5000 programmable logic device family data sheet notes to tables: (1) see operating requirements for altera devices data sheet in this data book. (2) minimum dc input is ?.3 v. during transitions, the inputs may undershoot to ?.0 v or overshoot to 7.0 v for periods shorter than 20 ns under no-load conditions. (3) numbers in parentheses are for industrial-temperature-range versions. (4) maximum v cc rise time for max 5000 devices is 10 ms. (5) typical values are for t a = 25 c and v cc = 5.0 v. (6) the i oh parameter refers to high-level ttl output current; the i ol parameter refers to low-level ttl output current. figure 6 shows typical output drive characteristics of max 5000 devices. figure 6. output drive characteristics of max 5000 devices timing model max 5000 epld timing can be analyzed with the max+plus ii software, with a variety of other industry-standard eda simulators and timing analyzers, or with the timing model shown in figure 7 . max 5000 eplds have fixed internal delays that allow the user to determine the worst-case timing for any design. max+plus ii provides timing simulation, point-to-point delay prediction, and detailed timing analysis for system-level performance evaluation. v o output voltage (v) 12345 20 40 60 100 80 0.45 v cc = 5.0 v i ol i oh room temp. i o output current (ma) typ.
altera corporation 323 max 5000 programmable logic device family data sheet figure 7. max 5000 timing model i/o delay t io logic array delay t lad input delay t in logic array control delay t lac feedback delay t fd output delay t od t xz t zx register delay t rd t comb t latch t clr t pre t su t h shared expander delay t sexp array clock delay t ic global clock delay t ics single-lab eplds pia delay t pia logic array delay t lad input delay t in logic array control delay t lac feedback delay t fd output delay t od t xz t zx register delay t rd t comb t latch t clr t pre t su t h i/o delay t io shared expander delay t sexp array clock delay t ic global clock delay t ics multi-lab eplds
324 altera corporation max 5000 programmable logic device family data sheet timing information can be derived from the timing model and parameters for a particular epld. external timing parameters are calculated with the sum of internal parameters and represent pin-to-pin timing delays. figure 8 shows the internal timing relationship for internal and external delay parameters. f for more information on epld timing, refer to application note 78 (understanding max 7000, max 5000 & classic timing) in this data book.
altera corporation 325 max 5000 programmable logic device family data sheet figure 8. switching waveforms t in high-impedance state output pin t xz t zx t od t rd t f t ch t cl t r t in t ics t su t h t f t r t ach t acl t in t ic t rd , t latch t fd t fd t pi a t io t sexp t od t comb t su t h t clr , t pre input mode array clock mode global clock mode output mode t lac, t lad i/o pin expander array delay logic array input logic array output output pin input pin clock into logic array data from logic array register output to local lab logic array register output to another lab clock pin clock from logic array global clock pin global clock at register data from logic array clock from logic array data from logic array in multi-lab eplds, i/o pins that are used as inputs traverse the pia. t r & t f < 3 ns. inputs are driven at 3 v for a logic high and 0 v for a logic low. all timing characteristics are measured at 1.5 v.
326 altera corporation max 5000 programmable logic device family data sheet epm5032 ac operating conditions note (1) external timing parameters epm5032-15 epm5032-20 epm5032-25 symbol parameter conditions min max min max min max unit t pd1 input to non-registered output c1 = 35 pf 15 20 25 ns t pd2 i/o input to non-registered output c1 = 35 pf 15 20 25 ns t su global clock setup time 9 12 15 ns t h global clock hold time 0 0 0 ns t co1 global clock to output delay c1 = 35 pf 10 12 15 ns t ch global clock high time 6 7 8 ns t cl global clock low time 6 7 8 ns t asu array clock setup time 5 6 8 ns t ah array clock hold time 5 6 8 ns t aco1 array clock to output delay c1 = 35 pf 15 18 22 ns t ach array clock high time note (3) 679ns t acl array clock low time 7 9 11 ns t odh output data hold time after clock c1 = 35 pf (2) 111ns t cnt min. global clock period 13 16 20 ns f cnt max. internal global clock frequency note (4) 76.9 62.5 50 mhz t acnt min. array clock period 13 16 20 ns f acnt max. internal array clock frequency note (4) 76.9 62.5 50 mhz f max max. clock frequency note (5) 83.3 71.4 62.5 mhz
altera corporation 327 max 5000 programmable logic device family data sheet internal timing parameters note (6) epm5032-15 epm5032-20 epm5032-25 symbol parameter conditions min max min max min max unit t in input pad and buffer delay 3 5 7 ns t io i/o input pad and buffer delay 3 5 7 ns t sexp expander array delay 8 10 15 ns t lad logic array delay 7 10 13 ns t lac logic control array delay 4 4 4 ns t od output buffer and pad delay c1 = 35 pf 4 4 4 ns t zx output buffer enable delay c1 = 35 pf 7 7 7 ns t xz output buffer disable delay c1 = 5 pf 7 7 7 ns t su register setup time 4 4 5 ns t latch flow-through latch delay 1 1 1 ns t rd register delay 1 1 1 ns t comb combinatorial delay 1 1 1 ns t h register hold time 5 8 10 ns t ic array clock delay 7 8 10 ns t ics global clock delay 2 2 3 ns t fd feedback delay 1 1 1 ns t pre register preset time 5 6 9 ns t clr register clear time 5 6 9 ns
328 altera corporation max 5000 programmable logic device family data sheet epm5064, epm5128, epm5130 & epm5192 ac operating conditions note (1) external timing parameters epm5064-1 epm5128-1 epm5130-1 epm5192-1 epm5064-2 epm5128-2 epm5064 epm5128 epm5130 epm5192 symbol parameter conditions min max min max min max unit t pd1 input to non-registered output c1 = 35 pf 25 30 35 ns t pd2 i/o input to non-registered output c1 = 35 pf 40 45 55 ns t su global clock setup time 15 20 25 ns t h global clock hold time 0 0 0 ns t co1 global clock to output delay c1 = 35 pf 14 16 20 ns t ch global clock high time 8 10 12.5 ns t cl global clock low time 8 10 12.5 ns t asu array clock setup time 5 6 10 ns t ah array clock hold time 6 8 10 ns t aco1 array clock to output delay c1 = 35 pf 25 30 35 ns t ach array clock high time note (3) 11 14 16 ns t acl array clock low time note (3) 91114ns t cnt min. global clock period 20 25 30 ns t odh output data hold time after clock c1 = 35 pf, note (2) 222ns f cnt max. internal global clock frequency note (4) 50 40 33.3 mhz t acnt min. array clock period 20 25 30 ns f acnt max. internal array clock frequency note (4) 50 40 33.3 mhz f max max. clock frequency note (3) 62.5 50 40 mhz
altera corporation 329 max 5000 programmable logic device family data sheet notes to tables: (1) operating conditions: v cc = 5 v 5 % , t a = 0 c to 70 c for commercial use. v cc = 5 v 10 % , t a = ?0 c to 85 c for industrial use. (2) this parameter is a guideline that is sample-tested only. it is based on extensive device characterization. this parameter applies for both global and array clocking. (3) this parameter is measured with a positive-edge-triggered clock at the register. for negative-edge clocking, the t ach and t acl parameters must be swapped. (4) for epm5032 devices, this parameter is measured with a 32-bit counter programmed into each lab. for epm5064, epm5128, epm5130, and epm5192 devices, this parameter is measured with a 16-bit counter programmed into each lab. i cc is characterized at 0 c. (5) the f max values represent the highest frequency for pipelined data. (6) for information on internal timing parameters, refer to application note 78 (understanding max 7000, max 5000 & classic timing) in this data book. internal timing parameters note (6) epm5064-1 epm5128-1 epm5130-1 epm5192-1 epm5064-2 epm5128-2 epm5064 epm5128 epm5130 epm5192 symbol parameter conditions min max min max min max unit t in input pad and buffer delay 5 7 11 ns t io i/o input pad and buffer delay 6 6 11 ns t sexp expander array delay 12 14 20 ns t lad logic array delay 12 14 14 ns t lac logic control array delay 10 12 13 ns t od output buffer and pad delay c1 = 35 pf 5 5 6 ns t zx output buffer enable delay c1 = 35 pf 10 11 13 ns t xz output buffer disable delay c1 = 5 pf 10 11 13 ns t su register setup time 6 8 12 ns t latch flow-through latch delay 3 4 4 ns t rd register delay 1 2 2 ns t comb combinatorial delay 3 4 4 ns t h register hold time 4 6 8 ns t ic array clock delay 14 16 16 ns t ics global clock delay 3 2 1 ns t fd feedback delay 1 1 2 ns t pre register preset time 5 6 7 ns t clr register clear time 5 6 7 ns t pia programmable interconnect array delay 14 16 20 ns
330 altera corporation max 5000 programmable logic device family data sheet figure 9 shows typical supply current versus frequency for max 5000 devices. figure 9. i cc vs. frequency for max 5000 devices (part 1 of 2) v cc = 5.0 v room temp. 100 hz 1 khz 10 khz 100 khz 1 mhz 10 mhz 40 120 frequency i cc active (ma) typ. 240 160 200 80 100 mhz epm5032 v cc = 5.0 v room temp. 100 hz 1 khz 10 khz 100 khz 1 mhz 10 mhz 50 frequency i cc active (ma) typ. 200 100 150 100 mhz 50 mhz epm5128 epm5130 v cc = 5.0 v room temp. 1 khz 10 khz 100 khz 1 mhz 10 mhz 100 frequency i cc active (ma) typ. 400 200 300 100 hz v cc = 5.0 v room temp. 1 khz 10 khz 100 khz 1 mhz 10 mhz 100 frequency i cc active (ma) typ. 500 200 300 50 mhz 400 100 hz epm5064
altera corporation 331 max 5000 programmable logic device family data sheet figure 9. i cc vs. frequency for max 5000 devices (part 2 of 2) device pin-outs tables 4 through 13 show the pin names and numbers for the pins in each max 5000 device package. v cc = 5.0 v room temp. 1 khz 10 khz 100 khz 1 mhz 10 mhz 100 frequency i cc active (ma) typ. 500 200 300 50 mhz 400 100 hz epm5192 table 4. epm5032 dedicated pin-outs pin name 28-pin j-lead 28-pin dip 28-pin soic input/clk 92 2 input 6, 7, 8, 20, 21, 22, 23 1, 13, 14, 15, 16, 27, 28 1, 13, 14, 15, 16, 27, 28 gnd 15, 28 8, 21 8, 21 vcc 1, 14 7, 22 7, 22
332 altera corporation max 5000 programmable logic device family data sheet table 5. epm5032 i/o pin-outs mc 28-pin j-lead 28-pin dip 28-pin soic mc 28-pin j-lead 28-pin dip 28-pin soic 110 3 3 17 24 17 17 2 18 311 4 4 19 25 18 18 4 20 512 5 5 21 26 19 19 6 22 713 6 6 23 27 20 20 8 24 9 16 9 9 25 2 23 23 10 26 11 17 10 10 27 3 24 24 12 28 13 18 11 11 29 4 25 25 14 30 15 19 12 12 31 5 26 26 16 32 table 6. epm5064 dedicated pin-outs pin name 44-pin j-lead input/clk 34 input 9, 11, 12, 13, 31, 33, 35 gnd 10, 21, 32, 43 vcc 3, 14, 25, 36
altera corporation 333 max 5000 programmable logic device family data sheet table 7. epm5064 i/o pin-outs mc lab 44-pin j-lead mc lab 44-pin j-lead 1a 2 17 b 15 2a 4 18 b 16 3a 5 19 b 17 4a 6 20 b 18 5a 7 21 b 19 6a 8 22 b 20 7a 23 b 22 8a 24 b 23 9a 25 b 10 a 26 b 11 a 27 b 12 a 28 b 13 a 29 b 14 a 30 b 15 a 31 b 16 a 32 b 33c2449d37 34c2650d38 35c2751d39 36c2852d40 37c2953d41 38c3054d42 39 c 55 d 44 40 c 56 d 1 41 c 57 d 42 c 58 d 43 c 59 d 44 c 60 d 45 c 61 d 46 c 62 d 47 c 63 d 48 c 64 d
334 altera corporation max 5000 programmable logic device family data sheet table 8. epm5128 dedicated pin-outs pin name 68-pin j-lead 68-pin pga input/clk 1b6 input 2, 32, 34, 35, 36, 66, 68 a6, l4, l5, l6, k6, a8, a7 gnd 16, 33, 50, 67 b7, e2, g10, k5 vcc 3, 20, 37, 54 b5, e10, g2, k7 table 9. epm5128 i/o pin-outs (part 1 of 3) mc lab 68-pin j-lead 68-pin pga mc lab 68-pin j-lead 68-pin pga 1 a 4 a5 17 b 12 c2 2 a 5 b4 18 b 13 c1 3 a 6 a4 19 b 14 d2 4 a 7 b3 20 b 15 d1 5 a 8 a3 21 b 17 e1 6a 9a222b 7 a 10 b2 23 b 8 a 11 b1 24 b 9 a 25 b 10 a 26 b 11 a 27 b 12 a 28 b 13 a 29 b 14 a 30 b 15 a 31 b 16 a 32 b
altera corporation 335 max 5000 programmable logic device family data sheet 33c18f249d24j2 34c19f150d25j1 35c21g151d26k1 36c22h252d27k2 37c23h153d28l2 38 c 54 d 29 k3 39 c 55 d 30 l3 40 c 56 d 31 k4 41 c 57 d 42 c 58 d 43 c 59 d 44 c 60 d 45 c 61 d 46 c 62 d 47 c 63 d 48 c 64 d 65 e 38 l7 81 f 46 j10 66 e 39 k8 82 f 47 j11 67 e 40 l8 83 f 48 h10 68 e 41 k9 84 f 49 h11 69 e 42 l9 85 f 51 g11 70 e 43 l10 86 f 71 e 44 k10 87 f 72 e 45 k11 88 f 73 e 89 f 74 e 90 f 75 e 91 f 76 e 92 f 77 e 93 f 78 e 94 f 79 e 95 f 80 e 96 f table 9. epm5128 i/o pin-outs (part 2 of 3) mc lab 68-pin j-lead 68-pin pga mc lab 68-pin j-lead 68-pin pga
336 altera corporation max 5000 programmable logic device family data sheet 97 g 52 f10 113 h 58 c10 98 g 53 f11 114 h 59 c11 99 g 55 e11 115 h 60 b11 100 g 56 d10 116 h 61 b10 101 g 57 d11 117 h 62 a10 102 g 118 h 63 b9 103 g 119 h 64 a9 104 g 120 h 65 b8 105 g 121 h 106 g 122 h 107 g 123 h 108 g 124 h 109 g 125 h 110 g 126 h 111 g 127 h 112 g 128 h table 10. epm5130 dedicated pin-outs pin name 84-pin j-lead 100-pin pga 100-pin pqfp input/clk 1c716 input 2, 5, 6, 7, 36, 37, 38, 41, 42, 43, 44, 47, 48, 49, 78, 79, 80, 83, 84 a5, a7, a8, a9, a10, b5, b7, b9, c6, l7, l8, m5, m7, m9, n4, n5, n6, n7, n9 9, 10, 11, 14, 15, 16, 17, 20, 21, 22, 59, 60, 61, 64, 65, 66, 67, 70, 71, 72 gnd 19, 20, 39, 40, 61, 62, 81, 82 b8, c8, f2, f3, h11, h12, l6, m6 12, 13, 37, 38, 62, 63, 87, 88 vcc 3, 4, 23, 24, 45, 46, 65, 66 a6, b6, f12, f13, h1, h2, m8, n8 18, 19, 43, 44, 68, 69, 93, 94 table 9. epm5128 i/o pin-outs (part 3 of 3) mc lab 68-pin j-lead 68-pin pga mc lab 68-pin j-lead 68-pin pga
altera corporation 337 max 5000 programmable logic device family data sheet table 11. epm5130 i/o pin-outs (part 1 of 2) mc lab 84-pin j-lead 100-pin pga 100-pin pqfp mc lab 84-pin j-lead 100-pin pga 100-pin pqfp 1 a 8 b13 1 17 b 14 a4 23 2 a 9 c12 2 18 b 15 b4 24 3 a 10 a13 3 19 b 16 a3 25 4 a 11 b12 4 20 b 17 a2 26 5 a 12 a12 5 21 b 18 b3 27 6 a 13 b11 6 22 b 21 a1 28 7 a a11 7 23 b b2 29 8 a b10 8 24 b b1 30 9a 25 b 10 a 26 b 11 a 27 b 12 a 28 b 13 a 29 b 14 a 30 b 15 a 31 b 16 a 32 b 33 c 22 c2 31 49 d 30 g3 41 34 c 25 c1 32 50 d 31 g1 42 35 c 26 d2 33 51 d 32 h3 45 36 c 27 d1 34 52 d 33 j1 46 37 c 28 e2 35 53 d 34 j2 47 38 c 29 e1 36 54 d 35 k1 48 39 c f1 39 55 d k2 49 40 c g2 40 56 d l1 50 41 c 57 d 42 c 58 d 43 c 59 d 44 c 60 d 45 c 61 d 46 c 62 d 47 c 63 d 48 c 64 d
338 altera corporation max 5000 programmable logic device family data sheet 65 e 50 m1 51 81 f 56 n10 73 66 e 51 l2 52 82 f 57 m10 74 67 e 52 n1 53 83 f 58 n11 75 68 e 53 m2 54 84 f 59 n12 76 69 e 54 n2 55 85 f 60 m11 77 70 e 55 m3 56 86 f 63 n13 78 71 e n3 57 87 f m12 79 72 e m4 58 88 f m13 80 73 e 89 f 74 e 90 f 75 e 91 f 76 e 92 f 77 e 93 f 78 e 94 f 79 e 95 f 80 e 96 f 97 g 64 l12 81 113 h 72 g11 91 98 g 67 l13 82 114 h 73 g13 92 99 g 68 k12 83 115 h 74 f11 95 100 g 69 k13 84 116 h 75 e13 96 101 g 70 j12 85 117 h 76 e12 97 102 g 71 j13 86 118 h 77 d13 98 103 g h13 89 119 h d12 99 104 g g12 90 120 h c13 100 105 g 121 h 106 g 122 h 107 g 123 h 108 g 124 h 109 g 125 h 110 g 126 h 111 g 127 h 112 g 128 h table 11. epm5130 i/o pin-outs (part 2 of 2) mc lab 84-pin j-lead 100-pin pga 100-pin pqfp mc lab 84-pin j-lead 100-pin pga 100-pin pqfp
altera corporation 339 max 5000 programmable logic device family data sheet table 12. epm5192 dedicated pin-outs pin name 84-pin j-lead 84-pin pga input/clk 1a6 input 2, 41, 42, 43, 44, 83, 84 a5, k6, j6, j7, l7, c7, c6 gnd 18, 19, 39, 40, 60, 61, 81, 82 a7, b7, e1, e2, g10, g11, k5, l5 vcc 3, 24, 45, 66 b5, e10, g2, k7 table 13. epm5192 i/o pin-outs (part 1 of 4) mc lab 84-pin j-lead 84-pin pga mc lab 84-pin j-lead 84-pin pga 1 a 4c517 b 12c2 2 a 5a418 b 13b1 3a 6b419b14c1 4a 7a320b15d2 5a 8a221 b 6a 9b322 b 7 a 10 a1 23 b 8 a 11 b2 24 b 9 a 25 b 10 a 26 b 11 a 27 b 12 a 28 b 13 a 29 b 14 a 30 b 15 a 31 b 16 a 32 b
340 altera corporation max 5000 programmable logic device family data sheet 33c16d149d22g3 34c17e350d23g1 35c20f251d25f1 36c21f352d26h1 37 c 53 d 38 c 54 d 39 c 55 d 40 c 56 d 41 c 57 d 42 c 58 d 43 c 59 d 44 c 60 d 45 c 61 d 46 c 62 d 47 c 63 d 48 c 64 d 65 e 27h281 f 31l1 66 e 28j182 f 32k2 67 e 29k183 f 33k3 68 e 30j284 f 34l2 69e 85f35l3 70e 86f36k4 71e 87f37l4 72e 88f38j5 73 e 89 f 74 e 90 f 75 e 91 f 76 e 92 f 77 e 93 f 78 e 94 f 79 e 95 f 80 e 96 f table 13. epm5192 i/o pin-outs (part 2 of 4) mc lab 84-pin j-lead 84-pin pga mc lab 84-pin j-lead 84-pin pga
altera corporation 341 max 5000 programmable logic device family data sheet 97 g 46 l6 113 h 54 j10 98 g 47 l8 114 h 55 k11 99 g 48 k8 115 h 56 j11 100 g 49 l9 116 h 57 h10 101 g 50 l10 117 h 102 g 51 k9 118 h 103 g 52 l11 119 h 104 g 53 k10 120 h 105 g 121 h 106 g 122 h 107 g 123 h 108 g 124 h 109 g 125 h 110 g 126 h 111 g 127 h 112 g 128 h 129 i 58 h11 145 j 64 f11 130 i 59 f10 146 j 65 e11 131 i 62 g9 147 j 67 e9 132 i 63 f9 148 j 68 d11 133 i 149 j 134 i 150 j 135 i 151 j 136 i 152 j 137 i 153 j 138 i 154 j 139 i 155 j 140 i 156 j 141 i 157 j 142 i 158 j 143 i 159 j 144 i 160 j table 13. epm5192 i/o pin-outs (part 3 of 4) mc lab 84-pin j-lead 84-pin pga mc lab 84-pin j-lead 84-pin pga
342 altera corporation max 5000 programmable logic device family data sheet 161 k 69 d10 177 l 73 a11 162 k 70 c11 178 l 74 b10 163 k 71 b11 179 l 75 b9 164 k 72 c10 180 l 76 a10 165 k 181 l 77 a9 166 k 182 l 78 b8 167 k 183 l 79 a8 168 k 184 l 80 b6 169 k 185 l 170 k 186 l 171 k 187 l 172 k 188 l 173 k 189 l 174 k 190 l 175 k 191 l 176 k 192 l table 13. epm5192 i/o pin-outs (part 4 of 4) mc lab 84-pin j-lead 84-pin pga mc lab 84-pin j-lead 84-pin pga
altera corporation 343 max 5000 programmable logic device family data sheet pin-out diagrams figures 10 through 14 show the package pin-out diagrams of max 5000 devices. figure 10. epm5032 package pin-out diagrams package outlines not drawn to scale. windows in ceramic packages only. figure 11. epm5064 package pin-out diagrams package outline not drawn to scale. windows in ceramic packages only. 28-pin dip input input/clk i/o i/o i/o i/o vcc gnd i/o i/o i/o i/o input input input input i/o i/o i/o i/o vcc gnd i/o i/o i/o i/o input input 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-pin soic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 input input/clk i/o i/o i/o i/o vcc gnd i/o i/o i/o i/o input input input input i/o i/o i/o i/o vcc gnd i/o i/o i/o i/o input input 28-pin j-lead i/o i/o i/o vcc gnd i/o i/o i/o input input input input/clk i/o i/o i/o i/o input input input input i/o i/o i/o vcc gnd i/o i/o i/o 5 6 7 8 9 10 11 4 3 2 1 28 27 26 12 13 14 15 16 17 18 25 24 23 22 21 20 19 epm5032 epm5032 epm5032 i/o i/o i/o vcc i/o i/o i/o gnd i/o i/o i/o i/o i/o input gnd input input input vcc i/o i/o i/o i/o i/o i/o vcc input input/clk input gnd input i/o i/o i/o i/o i/o gnd i/o i/o i/o vcc i/o i/o i/o 44-pin j-lead 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 epm5064
344 altera corporation max 5000 programmable logic device family data sheet figure 12. epm5128 package pin-out diagrams package outlines not drawn to scale. windows in ceramic packages only. figure 13. epm5130 package pin-out diagrams package outlines not drawn to scale. windows in ceramic packages only. 68-pin j-lead i/o i/o i/o i/o i/o i/o gnd i/o i/o i/o vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vcc i/o i/o i/o gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vcc input input/clk input gnd input i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input gnd input input input vcc i/o i/o i/o i/o i/o i/o 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 epm5128 68-pin pga l k j h g f e d c b a epm5128 bottom view 1 2 3 4 5 6 7 8 9 10 11 84-pin j-lead i/o i/o i/o i/o i/o i/o i/o gnd gnd i/o i/o vcc vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input input input vcc vcc input input/clk input input gnd gnd input input input i/o i/o i/o 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 i/o i/o i/o i/o i/o i/o i/o i/o vcc vcc i/o i/o gnd gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o input input input gnd gnd input input input input vcc vcc input input input i/o i/o i/o i/o 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 epm5130 100-pin pga n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 epm5130 bottom view epm5130 100-pin pqfp pin 1 pin 81 pin 51 pin 31
altera corporation 345 max 5000 programmable logic device family data sheet figure 14. epm5192 package pin-out diagrams package outlines not drawn to scale. windows in ceramic packages only. 84-pin j-lead i/o i/o i/o i/o i/o i/o gnd gnd i/o i/o i/o i/o vcc i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o vcc input input/clk input input gnd gnd i/o i/o i/o i/o i/o i/o 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 i/o i/o i/o i/o i/o i/o i/o i/o vcc i/o i/o i/o i/o gnd gnd i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o gnd gnd input input input input vcc i/o i/o i/o i/o i/o i/o i/o i/o 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 epm5192 84-pin pga l k j h g f e d c b a epm5192 bottom view 1 2 3 4 5 6 7 8 9 10 11
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